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542 commits

Author SHA1 Message Date
ReinUsesLisp e3534700d7 shader_ir/conversion: Split int and float selector and implement F2F H1 2019-08-28 16:09:33 -03:00
ReinUsesLisp b13fbc25b8 shader_ir/conversion: Implement F2I F16 Ra.H1 2019-08-27 23:40:40 -03:00
bunnei cedc1aab4a
Merge pull request #2753 from FernandoS27/float-convert 
Shader_Ir: Implement F16 Variants of F2F, F2I, I2F.
 2019-08-21 10:27:57 -04:00
ReinUsesLisp 2ff8044806 shader_ir: Implement NOP 2019-08-04 03:02:55 -03:00
bunnei 52f54c728d
Merge pull request #2592 from FernandoS27/sync1 
Implement GPU Synchronization Mechanisms & Correct NVFlinger
 2019-07-26 14:26:44 -04:00
bunnei 31e8a61527
Merge pull request #2743 from FernandoS27/surpress-assert 
Downgrade and suppress a series of GPU asserts and debug messages.
 2019-07-25 12:34:36 -04:00
bunnei 9be9600bdc
Merge pull request #2704 from FernandoS27/conditional 
maxwell3d: Implement Conditional Rendering
 2019-07-24 17:07:57 -04:00
bunnei f601f25bcc
Merge pull request #2734 from ReinUsesLisp/compute-shaders 
gl_rasterizer: Implement compute shaders
 2019-07-22 11:12:55 -04:00
bunnei 27e10e0442
Merge pull request #2735 from FernandoS27/pipeline-rework 
Rework Dirty Flags in GPU Pipeline, Optimize CBData and Redo Clearing mechanism
 2019-07-21 00:59:52 -04:00
Fernando Sahmkow 11f4e739bd Shader_Ir: Implement F16 Variants of F2F, F2I, I2F. 
This commit takes care of implementing the F16 Variants of the 
conversion instructions and makes sure conversions are done.
 2019-07-20 17:38:25 -04:00
Fernando Sahmkow 7a35178ee2 Maxwell3D: Reorganize and address feedback 2019-07-20 10:18:35 -04:00
ReinUsesLisp 6c4985edc9 shader/half_set_predicate: Implement missing HSETP2 variants 2019-07-19 22:20:47 -03:00
Fernando Sahmkow 3a3fee5abf MaxwellDMA/KeplerCopy: Downgrade DMA log message to Trace. 
This log was just to know which games used DMA. It's no longer 
important.
 2019-07-18 08:31:38 -04:00
Fernando Sahmkow 4be61013a1 GL_State: Feedback and fixes 2019-07-17 17:29:56 -04:00
Fernando Sahmkow 5ad889f6fd Maxwell3D: Address Feedback 2019-07-17 17:29:55 -04:00
Fernando Sahmkow 8cdbfe69b1 GL_Rasterizer: Corrections to Clearing. 2019-07-17 17:29:54 -04:00
Fernando Sahmkow 0ff4a5fa39 Maxwell3D: Correct marking dirtiness on CB upload 2019-07-17 17:29:53 -04:00
Fernando Sahmkow fec32fed18 GL_Rasterizer: Rework RenderTarget/DepthBuffer clearing 2019-07-17 17:29:52 -04:00
Fernando Sahmkow a081dea8ab Maxwell3D: Implement State Dirty Flags. 2019-07-17 17:29:51 -04:00
Fernando Sahmkow 0d3db58657 Maxwell3D: Rework CBData Upload 2019-07-17 17:29:50 -04:00
Fernando Sahmkow f2e7b29c14 Maxwell3D: Rework the dirty system to be more consistant and scaleable 2019-07-17 17:29:49 -04:00
Fernando Sahmkow e42bcf2314 maxwell3d: Implement Conditional Rendering 
Conditional Rendering takes care of conditionaly clearing or drawing
depending on a set of queries. This PR implements the query checks to
stablish if things can be rendered or not.
 2019-07-17 17:13:19 -04:00
ReinUsesLisp 725ba6cf63 gl_rasterizer: Implement compute shaders 2019-07-15 17:38:25 -03:00
Fernando Sahmkow 1bdb59fc6e
Merge pull request #2695 from ReinUsesLisp/layer-viewport 
gl_shader_decompiler: Implement gl_ViewportIndex and gl_Layer in vertex shaders
 2019-07-15 16:28:07 -04:00
bunnei 3477b92289
Merge pull request #2675 from ReinUsesLisp/opengl-buffer-cache 
buffer_cache: Implement a generic buffer cache and its OpenGL backend
 2019-07-14 19:03:43 -04:00
Fernando Sahmkow 0ec9da2f9f
Merge pull request #2692 from ReinUsesLisp/tlds-f16 
shader/texture: Add F16 support for TLDS
 2019-07-14 08:44:38 -04:00
Fernando Sahmkow 8a6fc529a9 shader_ir: Implement BRX & BRA.CC 2019-07-09 08:14:37 -04:00
ReinUsesLisp c9d886c84e gl_shader_decompiler: Implement gl_ViewportIndex and gl_Layer in vertex shaders 
This commit implements gl_ViewportIndex and gl_Layer in vertex and
geometry shaders. In the case it's used in a vertex shader, it requires
ARB_shader_viewport_layer_array. This extension is available on AMD and
Nvidia devices (mesa and proprietary drivers), but not available on
Intel on any platform. At the moment of writing this description I don't
know if this is a hardware limitation or a driver limitation.

In the case that ARB_shader_viewport_layer_array is not available,
writes to these registers on a vertex shader are ignored, with the
appropriate logging.
 2019-07-07 20:42:55 -03:00
ReinUsesLisp d0966b9f7c shader/texture: Add F16 support for TLDS 2019-07-07 16:05:56 -03:00
ReinUsesLisp 7ecf64257a gl_rasterizer: Minor style changes 2019-07-06 00:37:55 -03:00
Fernando Sahmkow 82b829625b video_core: Implement GPU side Syncpoints 2019-07-05 15:49:11 -04:00
ReinUsesLisp 4d63f97945 shader_bytecode: Include missing <array> 2019-06-24 01:51:02 -03:00
Fernando Sahmkow 082740d34d surface: Correct format S8Z24 2019-06-20 21:38:34 -03:00
Fernando Sahmkow 7232a1ed16 decoders: correct block calculation 2019-06-20 21:38:34 -03:00
Fernando Sahmkow cb728797b0 fermi2d: Correct Origin Mode 2019-06-20 21:38:34 -03:00
Fernando Sahmkow 175aa343ff texture_cache: Fermi2D reform and implement View Mirage 
This also does some fixes on compressed textures reinterpret and on the
Fermi2D engine in general.
 2019-06-20 21:38:33 -03:00
ReinUsesLisp 06c4ce8645 shader: Decode SUST and implement backing image functionality 2019-06-20 21:38:33 -03:00
ReinUsesLisp b8c75a845b maxwell_3d: Partially implement texture buffers as 1D textures 2019-06-20 21:36:12 -03:00
ReinUsesLisp 4e81fc8296 shader: Implement texture buffers 2019-06-20 21:36:12 -03:00
Fernando Sahmkow d267948a73 texture_cache: loose TryReconstructSurface when accurate GPU is not on. 
Also corrects some asserts.
 2019-06-20 21:36:12 -03:00
Fernando Sahmkow 6bd034eae9 engine_upload: Addapt to new Texture Cache 2019-06-20 21:36:12 -03:00
ReinUsesLisp 345e73f2fe video_core: Use un-shifted block sizes to avoid integer divisions 
Instead of storing all block width, height and depths in their shifted
form:

block_width = 1U << block_shift;

Store them like they are provided by the emulated hardware (their
block_shift form). This way we can avoid doing the costly
Common::AlignUp operation to align texture sizes and drop CPU integer
divisions with bitwise logic (defined in Common::AlignBits).
 2019-06-20 21:36:12 -03:00
bunnei c7b5c245e1
Merge pull request #2562 from ReinUsesLisp/split-cbuf-upload 
video_core/engines: Move ConstBufferInfo out of Maxwell3D
 2019-06-17 22:35:04 -04:00
ReinUsesLisp 528c15051c kepler_compute: Use std::array for cbuf info 2019-06-07 20:36:22 -03:00
ReinUsesLisp 17d5fb6d06 kepler_compute: Fix block_dim_x encoding 2019-06-07 20:35:46 -03:00
ReinUsesLisp 2f2a61887a video_core/engines: Move ConstBufferInfo out of Maxwell3D 2019-06-07 19:47:15 -03:00
Fernando Sahmkow a32c52b1d8 shader_bytecode: Mark EXIT as flow instruction 2019-06-04 12:18:35 -04:00
ReinUsesLisp 75e7b45d69 shader/memory: Implement ST (generic memory) 2019-05-20 22:41:53 -03:00
ReinUsesLisp f78ef617b6 shader/memory: Implement LD (generic memory) 2019-05-20 22:38:59 -03:00
bunnei d49efbfb4a
Merge pull request #2441 from ReinUsesLisp/al2p 
shader: Implement AL2P and ALD.PHYS
 2019-05-19 14:02:58 -04:00